Process to reduce substrate effects by forming channels under inductor devices and around analog blocks

ABSTRACT

A first method of reducing semiconductor device substrate effects comprising the following steps. O + or O 2   + are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

This is a continuation of patent application Ser. No. 10/225,828, filingdate Aug. 22, 2002, now U.S. Pat. No. 6,869,884, A Process To ReduceSubstrate Effects By Forming Channels Under Inductor Devices And AroundAnalog Blocks, assigned to the same assignee as the present invention,which is herein incorporated by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates generally to fabrication of semiconductordevices, and more specifically to methods of reducing substrate effectsunder inductor devices and around analog blocks.

BACKGROUND OF THE INVENTION

Inductor quality (Q) is very often reduced by substrate eddy current,i.e. image current. Similarly, analog devices are very sensitive tonoise generated by the underlying silicon substrate, i.e. substrateeffects.

U.S. Pat. No. 6,180,995 B1 to Hebert describes a process to etch atrench in a substrate under an inductor.

U.S. Pat. No. 6,313,008 B1 to Leung et al. describes a trench formed byan implant and isotropic etch process.

U.S. Pat. No. 6,326,314 B1 to Merrill et al. describes an inductorprocess with a trench in a substrate.

U.S. Pat. No. 6,287,931 B1 to Chen describes an inductor process with atrench in an insulating layer.

U.S. Pat. No. 6,057,202 to Chen et al. describes a trench underinductors.

U.S. Pat. No. 5,539,241 to Abidi et al. and U.S. Pat. No. 5,600,174 toReay et al. each describe inductor processes with trenches underlyingthe structure.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provideimproved methods of reducing substrate effects under inductor devicesand around analog blocks.

Other objects will appear hereinafter.

It has now been discovered that the above and other objects of thepresent invention may be accomplished in the following manner.Specifically, in a first method of reducing semiconductor devicesubstrate effects, O⁺or O₂ ⁺are selectively implanted into a siliconsubstrate to form a silicon-damaged silicon oxide region. One or moredevices are formed over the silicon substrate proximate thesilicon-damaged silicon oxide region within at least one dielectriclayer. A passivation layer is formed over the at least one upperdielectric layer. The passivation layer and the at least one upperdielectric layer are patterned to form a trench exposing a portion ofthe silicon substrate over the silicon-damaged silicon oxide region. Thesilicon-damaged silicon oxide region is selectively etched to form achannel continuous and contiguous with the trench whereby the channelreduces the substrate effects of the one or more semiconductor devices.A second method of reducing substrate effects under analog devicesincludes forming an analog device on a SOI substrate and thenselectively etching the silicon oxide layer of the SOI substrate to forma channel at least partially underlying the analog device.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention will be moreclearly understood from the following description taken in conjunctionwith the accompanying drawings in which like reference numeralsdesignate similar or corresponding elements, regions and portions and inwhich:

FIGS. 1 to 5 schematically illustrate in cross-sectional representationa first preferred embodiment of the present invention.

FIGS. 6 to 8 schematically illustrate in cross-sectional representationa second preferred embodiment of the present invention.

FIG. 9 schematically illustrates a plan view incorporating the structureof FIG. 8 along line 8-8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First PreferredEmbodiment- FIGS. 1 to 5

Initial Structure

FIG. 1 illustrates a cross-sectional view of a silicon substrate 10 thatis preferably a semiconductor substrate.

A first patterned masking layer 12 is formed over silicon substrate 10leaving a portion 14 of silicon substrate 10 exposed. First maskinglayer 12 is preferably comprised of photoresist.

Using the first patterned masking layer 12 as a mask, an oxygen implant16 is implanted into silicon substrate 10 to a depth of preferably fromabout 1000 to 20,000 Å and more preferably from about 5000 to 10,000 Åto form a silicon-damaged silicon oxide (SiO₂) portion 18 within siliconsubstrate 10. The oxygen implant 16 is either an O⁺ or an O₂ ⁺ implantand is conducted at a dose of preferably from about 1E16 to 1E17ions/cm² and more preferably from about 4E16 to 8E16 ions/cm².

Silicon-damaged portion 18 has a maximum width 20 of preferably fromabout 8 to 52 μm and more preferably about 10 to 50 μm.

Formation of ILD Layer 24

As shown in FIG. 2, first patterned masking layer 12 is removed, thestructure is cleaned as necessary and a metal-oxide semiconductor (MOS)device 22 may be formed upon silicon substrate 10 adjacentsilicon-damaged silicon oxide portion 18.

An interlayer dielectric (ILD) layer 24 is formed over silicon substrate10 and over any semiconductor devices 22 formed upon silicon substrate10 to a thickness of preferably from about 4000 to 12,000 Å and morepreferably from about 6000 to 10,000 Å. ILD layer 24 is preferablyformed of thick field oxide, boron phosphorus silicon glass (BPSG),PECVD TEOS oxide, APCVD 0 ₃/TEOS oxide or HDP oxide and is morepreferably BPSG doped oxide.

ILD layer 24 may also include interconnect structures and othersemiconductor devices (not shown).

Formation of Inductor 28 Within Dielectric Layer 26

As shown in FIG. 2, a second IMD dielectric layer 26 is formed over theILD layer 24 and an inductor 28 may be formed with the second/upperdielectric layer 26 adjacent the silicon-damaged silicon oxide portion18 in conjunction with, or in place of, the semiconductor device 22.

IMD dielectric layer 26 is preferably comprised of an HDP oxide/TEOSoxide sandwich, PECVD SiH₄ oxide, PECVD TEOS oxide or HDP oxide (for gapfill) and is more preferably an HDP oxide/TEOS oxide sandwich.Dielectric layer 26 has a thickness of preferably from about 4000 to12,000 Å and more preferably from about 6000 to 10,000 Å.

Formation of Passivation Layer 30

Passivation layer 30 is then formed over IMD dielectric layer 26.Passivation layer 30 preferably comprises a lower 2% PSG layer 31 havinga thickness of preferably from about 2000 to 4000 Å and more preferablyfrom about 2500 to 3500 Å and an upper, overlying nitride or siliconnitride layer 33 having a thickness of preferably from about 3000 to8000 and more preferably from about 4000 to 6000 Å.

Etching of Trench 34

As shown in FIG. 3, a second patterned masking layer 32 is formed overpassivation layer 30 and, using the second patterned masking layer as amask, passivation layer 30, IMD dielectric layer 26 and ILD layer 24 areetched over silicon-damaged silicon oxide portion 18 forming trench 34and exposing a portion 35 of silicon substrate 10 roughly centered oversilicon-damaged silicon oxide portion 18.

Trench 34 is preferably formed using a reactive ion etch (RIE), an highdensity plasma (HDP) oxide etch or an inductive couple plasma (ICP) etchand more preferably an RIE oxide etch to save cost.

Formation of Channel 36

As shown in FIG. 4, an isotropic etch is used to etch out thesilicon-damaged silicon oxide portion 18 to form trench/channel 36.Preferably from about 10 to 50 μm of silicon substrate 10 adjacentsilicon-damage silicon oxide portion 18 is also removed to create awider channel 36. Channel 36 has a maximum width 37 of from about 50 to500 μm.

The formation of trench 34 and channel 36 reduces the substrate noiseeffect on the MOS device 22 and, if formed, also reduces the substrateeffect on the inductor 28 quality factor (Q). With the formation ofinductor 28/dielectric layer 26, a system-on-chip onnon-silicon-on-insulator (SOI) substrate is formed.

Formation of Uppermost Sealing Layer 38

As shown in FIG. 5, an optional uppermost sealing layer 38 may then beformed over patterned passivation layer 30′, sealing or closing offtrench 34. Uppermost sealing layer 38 is preferably formed to athickness of from about 3000 to 7000 Å and more preferably from about3000 to 6000 Å. Sealing layer 38 is preferably comprised of PECVDnitride or PECVD silicon nitride (to minimize wafer scratching). It isnoted that optional uppermost sealing layer 38 may not be necessary.

Second Embodiment - FIGS. 6 to 9

Initial Structure

FIG. 6 illustrates a cross-sectional view of a silicon-on-insulator(SOI) substrate 51 over silicon substrate 50 that is preferably asemiconductor substrate. A silicon oxide (SiO₂) layer 52 is formed oversilicon substrate 50 to a thickness of preferably from about 500 to 2000Å and more preferably from about 500 to 1500 Å. A second silicon layer54 is then formed over SiO₂ layer 52 to a thickness of preferably fromabout 500 to 2000 Å and more preferably from about 500 to 1500 Å.

A MOS device 56 may be formed upon SOI substrate 54 and an analog devicerepresented as at 60 is formed within ILD layer 58. ILD layer 58 may becomprised of multiple layers and is preferably comprised of PECVD TEOSoxide, PECVD SiH₄ oxide, HDP oxide or a low-k dielectric material and ismore preferably comprised of a low-k dielectric material.

A passivation layer 62 is formed over ILD layer 58. Passivation layer 62preferably comprises a lower 2% PSG layer 61 having a thickness ofpreferably from about 2000 to 4000 Å and more preferably from about 2500to 3500 Å and an upper, overlying nitride or silicon nitride layer 63having a thickness of preferably from about 3000 to 8000 and morepreferably from about 4000 to 6000 Å.

Formation of Trench 66

A first patterned masking layer 64 is formed over passivation layer 62and is preferably comprised of photoresist having a thickness ofpreferably from about 8000 to 22,000 Å and more preferably from about12,000 to 18,000.

As shown in FIG. 6, using first patterned masking layer 64 as a mask,passivation layer 62, ILD layer 58 and silicon layer/SOI substrate 54are patterned to form trench 66 exposing a portion 67 of SiO₂ layer 52adjacent analog device 60 and MOS 56.

Formation of Channel 70

As shown in FIG. 7, first patterned masking/photoresist layer 64 isremoved, preferably by a plasma O₂resist strip (PRS) followed by achemical resist strip (CRS) using a sulfuric peroxide mixture.

Then, as shown in FIG. 7, a second patterned masking layer 68 isdeposited over patterned passivation layer 62′, over the side walls oftrench 66 and partially over the exposed portion 67 of SiO₂ layer 52.Second patterned masking layer 68 is preferably comprised of nitride orsilicon nitride and has a thickness of preferably from about 1500 to2000 Å and more preferably from about 1750 to 2250 Å.

Formation of Sidewall Spacers 71

As shown in FIG. 8, second patterned masking nitride/silicon nitridelayer 68 is etched to form sidewall spacers 71 over the side walls oftrench 66, to protect the side walls of trench 66.

A wet etch process is then used to etch channel 70 within SiO₂ layer 52through second patterned masking layer opening 69/sidewall spacers 71.The wet etch process preferably employs a 10:1 dilute HF solution.

Channel 70 extends under at least a portion of analog device 60 andunder MOS device 56. Channel 70 has a width of preferably from about 50to 250 μm and more preferably from about 100 to 200 μm.

The formation of channel 70 reduces the substrate noise effect on theanalog device 60 and MOS device 56.

FIG. 9 is an overhead plan view of a system-on-chip 80 incorporatinganalog device 60 with trench 66 and channel 70 formed around itsperiphery. FIG. 8 is a cross-sectional view of FIG. 9 alone line 8-8.System-on-chip 80 also includes a central processing unit (CPU) 82,memory 84 and graphic device 86.

Advantages of the Invention

The advantages of one or more embodiments of the present inventioninclude:

-   1) reduction of substrate effects, i.e. noise reduction, for the    inductor devices;-   2) increased inductor quality (Q factor) by reduction of the    substrate eddy current; and-   3) to provide the environment for multi-functional chips on the same    substrate, i.e., e.g., system-on-chip.

While particular embodiments of the present invention have beenillustrated and described, it is not intended to limit the invention,except as defined by the following claims.

1. A semiconductor structure, comprising: a semiconductor substratehaving an unfilled channel formed therein; at least one semiconductordevice formed adjacent the unfilled channel; one or more dielectriclayers formed over the semiconductor substrate and the at least onesemiconductor device; a passivation layer over the one or moredielectric layers; and a trench extending through: the passivationlayer; and the one or more dielectric layers to the unfilled channel,the trench being continuous and contiguous with the unfilled channelwherein the unfilled channel reduces the substrate effects of the atleast one semiconductor device.
 2. The structure of claim 1, furthercomprising an uppermost sealing layer over the passivation layer.
 3. Thestructure of claim 1, further comprising an uppermost sealing layer overthe passivation layer; the uppermost sealing layer being comprised ofPECVD nitride or PECVD silicon nitride.
 4. The structure of claim 1,further comprising an uppermost sealing layer over the passivationlayer, sealing the trench from the ambient atmosphere; the uppermostsealing layer being comprised of PECVD silicon nitride.
 5. The structureof claim 1, wherein the one or more dielectric layers are comprised ofboron phosphorus silicon glass (BPSG), PECVD TEOS oxide, APCVD O₃/TEOSoxide or HDP oxide.
 6. The structure of claim 1, wherein the one or moredielectric layers are comprised of BPSG doped oxide.
 7. The structure ofclaim 1, wherein the one or more dielectric layers comprise: a lowerdielectric layer comprised of boron phosphorus silicon glass (BPSG),PECVD TEOS oxide, APCVD O₃/TEOS oxide or HDP oxide; and an upperdielectric layer comprised of an HDP oxide/TEOS oxide sandwich, PECVDSiH₄ oxide, PECVD TEOS oxide or HDP oxide.
 8. The structure of claim 1,wherein the one or more dielectric layers comprise: a lower dielectriclayer comprised of BPSG doped oxide; and an upper dielectric layercomprised of an HDP oxide/TEOS oxide sandwich.
 9. The structure of claim1, wherein the at least one semiconductor device is at least one MOSdevice.
 10. The structure of claim 1, wherein the at least onesemiconductor device is at least one inductor.
 11. The structure ofclaim 1, wherein the at least one semiconductor device is one or moreMOS devices and one or more inductors.
 12. The structure of claim 1,wherein the passivation layer is comprised of a lower layer and an upperlayer.
 13. The structure of claim 1, wherein the passivation layer iscomprised of a lower PSG layer and an upper nitride or silicon nitridelayer.
 14. The structure of claim 1, wherein the passivation layer iscomprised of: a lower PSG layer having a thickness of from about 2000 to4000 Å; and an upper nitride or silicon nitride layer having a thicknessof from about 3000 to 8000 Å.
 15. The structure of claim 1, wherein thepassivation layer is comprised of: a lower PSG layer having a thicknessof from about 2500 to 3500 Å; and an upper nitride or silicon nitridelayer having a thickness of from about 4000 to 6000 Å.
 16. The structureof claim 1, wherein the channel has a maximum width of from about 50 to500 μm.
 17. The structure of claim 1, wherein the at least onesemiconductor device forms part of a analog device on a chip, theunfilled channel being located around a periphery of the analog device.18. A semiconductor structure, comprising: a substrate; a silicon oxidelayer over the substrate; the silicon oxide layer having an unfilledchannel formed therein; a silicon layer upon the silicon oxide layer;one or more dielectric layers formed over the silicon oxide layer; theone or more dielectric layers including at least one semiconductordevice adjacent the unfilled channel; a passivation layer formed overthe one or more dielectric layers; and a trench extending through: thepassivation layer; the one or more dielectric layers and the siliconlayer to the unfilled channel the trench being continuous and contiguouswith the unfilled channel wherein the unfilled channel reduces thesubstrate effects of the at least one semiconductor device.
 19. Thestructure of claim 18, wherein the channel exposes at least a portion ofthe substrate.
 20. The structure of claim 18, wherein the substrate is asilicon substrate.
 21. The structure of claim 18, wherein the siliconoxide layer has a thickness of from about 500 to 2000 Å and the siliconlayer has a thickness of from about 500 to 2000 Å.
 22. The structure ofclaim 18, wherein the silicon oxide layer has a thickness of from about500 to 1500 Å and the silicon layer has a thickness of from about 500 to1500 Å.
 23. The structure of claim 18, wherein the passivation layer iscomprised of a lower layer and an upper layer.
 24. The structure ofclaim 18, wherein the passivation layer is comprised of a lower PSGlayer and an upper nitride or silicon nitride layer.
 25. The structureof claim 18, wherein the passivation layer is comprised of: a lower PSGlayer having a thickness of from about 2000 to 4000 Å; and an uppernitride or silicon nitride layer having a thickness of from about 3000to 8000 Å.
 26. The structure of claim 18, wherein the passivation layeris comprised of: a lower PSG layer having a thickness of from about 2500to 3500 Å; and an upper nitride or silicon nitride layer having athickness of from about 4000 to 6000 Å.
 27. The structure of claim 18,wherein the channel extends at least partially under the at least onesemiconductor device.
 28. The structure of claim 18, wherein the atleast one semiconductor device is an analog device.
 29. The structure ofclaim 28, further comprising a MOS device on the substrate proximate theanalog device, whereby the channel extends at least partially under theMOS device.
 30. The structure of claim 18, wherein the one or moredielectric layers are ILD layers.
 31. The structure of claim 18, whereinthe one or more dielectric layers are comprised of PECVD TEOS oxide,PECVD SiH₄ oxide, HDP oxide or a low-k dielectric material.
 32. Thestructure of claim 18, wherein the one or more dielectric layers arecomprised of a low-k dielectric material.
 33. The structure of claim 18,wherein the channel has a width of from about 50 to 250 μm.
 34. Thestructure of claim 18, wherein the channel has a width of from about 100to 200 μm.